After depositing a material, such as a metal to form an interconnect, over a semiconductor substrate, the material is planarized using chemical mechanical polishing (CMP). However, the resulting topography after planarization is nonuniform across the semiconductor substrate.
To increase uniformity, many methods focus on the difference in layout density between areas on a semiconductor substrate. Furthermore, the methods focus on increasing the feature density in low density areas by forming tiles in order to increase the polishing rates. Solutions include adding material (i.e., tiles or dummy features) between areas having different densities, trying to balance the density of various areas, placing features far apart and forming tiles between them or to increase the spacing between subsequently formed metal layers to decrease the risk of leakage between them. However, these methods increase the area needed for the features (e.g., the interconnects) making it difficult to decrease the overall size of a semiconductor die. Furthermore, nonuniformity is often not improved. Thus, a need exists for a method to improve uniformity without increasing the area need for placement of the features.
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